The “brain” of the computer is the CPU. It brings instructions from memory and carries out them. The fundamental cycle of every CPU is to bring the first instruction from memory, interpret it to decide its type and operands, execute it, and then bring, decode, and carry out following instructions. The cycle is repeated until the program comes to an end. Thus, programs are executed.
Each CPU has a particular set of instructions that it can implement. Therefore a Pentium cannot carry out SPARC programs and a SPARC cannot carry out Pentium programs. Because accessing memory to get an instruction or data word takes much longer than executing an instruction, all CPUs include some registers inside to hold key variables and temporary results. Therefore the instruction set generally contains instructions to load a word from memory into a register, and store a word from a register into memory. Other instructions merge two operands from registers, memory, or both into a result, such as adding two words and storing the result in a register or in memory.
In addition to the general registers used to hold variables and temporary results, most computers have some special registers that are visible to the programmer. One of these is the program counter, which contains the memory address of the next instruction to be obtained. After that instruction has been obtained, the program counter is updated to point to its successor.
Another register is the stack pointer, which points to the top of the current stack in memory. The stack includes one frame for each procedure that has been entered but not yet exited. A procedure’s stack frame holds those input parameters, local variables, and temporary variables that are not kept in registers.
Yet another register is the PSW (Program Status Word). This register includes the condition code bits, which are set by comparison instructions, the CPU priority, the mode (user or kernel), and various other control bits. User programs may normally read the entire PSW but normally may write only some of its fields. The PSW plays an important role in system calls and I/0.
The operating system must be well-informed of all the registers. When time multiplexing the CPU, the operating system will frequently stop the running program to (re)start another one. Every time it stops a running program, the operating system must save all the registers so they can be restored when the program runs later.
For getting better performance, CPU designers have long abandoned the simple model of bringing, decoding, and implementing one instruction at a time. A lot of modern CPUs have facilities for executing more than one instruction simultaneously. For instance, a CPU might have separate fetch, decode, and execute units, so that while it was executing instruction n, it could also be decoding instruction n + 1 and fetching instruction n + 2. Such an organization is called a pipeline and is illustrated in the following figure (a) for a pipeline with three stages. Longer pipelines are common. In most pipeline designs, once an instruction has been fetched into the pipeline, it must be executed, even if the preceding instruction was a conditional branch that was taken. Pipelines cause compiler writers and operating system writers great headaches because they disclose the complications of the underlying machine to them.